In recent years, the semiconductor industry has experienced rapid growth due to continuous improvement in integration density of various electronic components, e.g., transistors, diodes, resistors, capacitors, etc. For the most part, this improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area.
These smaller electronic components also require smaller packages that occupy less area than previous packages. Examples of types of packages for semiconductors include quad flat packages (QFP), pin grid array (PGA) packages, ball grid array (BGA) packages, flip chips (FC), three-dimensional integrated circuits (3DICs), wafer level packages (WLPs), and package on package (PoP) devices, etc. A multi-chip wafer level package has emerged to further reduce the physical size of a package. However, there are many challenges related to such multi-chip wafer level package.